国家/地区 中国（4）
IPC部 H（4）
IPC大类 H01（4）
IPC小类 H01L（4）
IPC H01L021/336（2） H01L029/16（2）
发明人 PENG S（4）
公开年 2013（4）
申请年 2013（4） 
专利权人 INST MICROELECTRONICS CHINESE ACAD SCI（4）

Graphene oxide top gate FET device parasitic resistance reducing method, involves covering gate-source, forming metal lead contact, and adjusting distance between gate-source and gate drain to reduce channel access resistance.

CHEN J, JIN Z, MA P, PENG S, ZHANG D, SHI J

Graphene field effect transistor, has insulating layer formed on semiconductor substrate, and gate electrode located on gate dielectric layer, which is provided with graphene oxide medium layer and metal oxide dielectric layer.

JIN Z, ZHANG D, CHEN J, MA P, PENG S, SHI J

Self-aligned graphene FET, has grid metal layer formed with gate dielectric layer, and self-aligned metal layer covered on source electrode, drain electrode, conductive channel and grid metal layer.

JIN Z, ZHANG D, CHEN J, MA P, PENG S, SHI J

Method for reducing graphene material and contact resistance of metal interconnection structure, involves providing structure using multi-layer graphene in contact area of graphene material and metal using single-layer graphene.

JIN Z, CHEN J, MA P, PENG S, WANG X