国家/地区 美国（5）
IPC部 H（5）
IPC大类 H01（5）
IPC小类 H01L（5）
IPC H01L021/04（2） H01L029/15（2） H01L029/16（2）
H01L029/78（2）
发明人 KRIVOKAPIC Z（5）
公开年 2010（3）
申请年 2008（3） 
专利权人 ADVANCED MICRO DEVICES INC（5）

Method for forming graphene liner and capping layer on conductive line/via of e.g. application specific integrated circuit device, involves performing chemical mechanical polishing process to remove excess amounts of copper-based material.

RYAN E T, KRIVOKAPIC Z, ZHANG X, WITT C, HE M, ZHAO L, WURTH C

Sidewall graphene device for three-dimensional electronics, has graphene layer that is provided on sidewall surface with varying width dimension and length dimension corresponding to height dimension and length dimension of surface.

CHEN A, KRIVOKAPIC Z

Method for fabricating graphene-based device e.g. FET for electronic application, involves forming graphene layer over FET and forming protective layer over graphene layer.

CHEN A, KRIVOKAPIC Z

Method for forming graphene-based FET device involves forming graphene layer within trench in substrate, to provide device structure such as FET.

CHEN A, KRIVOKAPIC Z

Sidewall graphene device fabricating process, involves forming protruding or mesa structure with sidewall surface, and forming device structure in contact with material layer in fin FET configuration.

CHEN A, KRIVOKAPIC Z