国家/地区 日本（5） 美国（5）
IPC部 H（5） B（3） C（3）
IPC大类 H01（5） B82（3） C01（2）
IPC小类 H01L（5） B82Y（3） C01B（2）
IPC H01L021/768（5） H01L023/532（5） H01L021/3205（4）
B82Y030/00（2） B82Y040/00（2） C01B031/02（2）
H01L021/02（2） H01L023/48（2） H01L023/52（2）
H01L029/06（2）
发明人 KAJITA A（5）
公开年 2014（3）
申请年 2013（3） 
专利权人 WADA M（5）

Semiconductor device, has carbon nanotubes that are formed so that graphene layers are stacked in state in which are inclined depthwise with respect to groove and are doped with one element from sidewalls of carbon nanotubes.

SAITO T, WADA M, ISOBAYASHI A, KAJITA A, MIYAZAKI H, SAKAI T

Semiconductor device has metal interconnect and graphene interconnect that are stacked to one another.

SAKATA A, KITAMURA M, WADA M, KATAGIRI M, YAMAZAKI Y, KAJITA A

Semiconductor device has lower-layer contact which is connected to undersurface side of first multi-layered graphene wire while upper-layer contact is connected to upper surface side of second multi-layered graphene wire.

WADA M, MIYAZAKI H, KAJITA A, ISOBAYASHI A, SAITO T, SAKAI T

Semiconductor device, has roll form graphene layer formed to surround catalyst metal layer and for growing with side surface of catalyst metal layer to set as growth origin, where facet is formed on side surface of catalyst metal layer.

WADA M, YAMAZAKI Y, KAJITA A, ISOBAYASHI A, SAITO T

Manufacturing method of semiconductor device, involves forming graphene layer on catalyst layer after planarizing exposed surface of catalyst layer by oxidation-treating.

YAMAZAKI Y, KATAGIRI M, SAKAI T, SAKUMA H, KITAMURA M, SAKATA A, WADA M, KAJITA A, MIZUSHIMA I, SAKUMA N