国家/地区 美国（5） 中国（2）
IPC部 H（5）
IPC大类 H01（5）
IPC小类 H01L（5）
IPC H01L029/16（3） H01L021/02（2） H01L021/768（2）
发明人 GRILL A（5）
公开年 2013（5）
申请年 2012（3）  2013（2） 
专利权人 INT BUSINESS.（5）

Method for forming interconnect structure for integrated microelectronic circuit, involves transferring graphene from copper foil, and patterning graphene, so that edges are coincided with vertical sidewall surfaces of copper structure.

BONILLA G, DIMITRAKOPOULOS C D, GRILL A, HANNON J B, LIN Q, NEUMAYER D A, OIDA S, OTT J A, PFEIFFER D

Interconnect structure for integrated microelectronic circuit, has graphene cap which is provided with edges that are vertically coincident with edges of copper structure.

BONILLA G, DIMITRAKOPOULOS C D, GRILL A, HANNON J B, LIN Q, NEUMAYER D A, OIDA S, OTT J A, PFEIFFER D, DIMITRAKOPOULOS C, HANNON J, NEUMAYER D, OTT J, DIMITRAKO P C D, GREER A

Forming graphene layer directly on a substrate e.g. single crystalline sapphire substrate which is used in structure, comprises depositing carbon atoms that form graphene layer on top surface of substrate.

CHU J O, DIMITRAKOPOULOS C D, FREITAG M O, GRILL A, MCARDLE T J, WISNIEFF R L

Semiconductor structure for semiconductor device, has substrate, graphene layer and double layer gate dielectric having alternate lamination of silicon nitride layer and hafnium oxide layer.

DIMITRAKOPOULOS C D, FARMER D B, GRILL A, LIN Y, NEUMAYER D A, PFEIFFER D, ZHU W, DIMITRAKOPOULOS C

Semiconductor structure used in e.g. cellular phone, personal computer, has ordered array of parallel graphene nanoribbons located on upper surface of substrate.

DIMITRAKOPOULOS C D, GRILL A, MCARDLE T J