国家/地区 美国（5）
IPC部 H（5）
IPC大类 H01（5）
IPC小类 H01L（5）
IPC H01L021/027（2） H01L021/306（2） H01L021/3205（2）
H01L021/3213（2） H01L021/768（2） H01L029/08（2）
H01L029/66（2） H01L029/78（2）
发明人 REN H（5）
公开年 2021（4）
申请年 2020（3） 
专利权人 GLOBALFOUNDR.（3） APPLIED MATE.（2）

Method for forming interconnect structure involves etching lithographic patterning structure to form partially patterned structure having first conductive lines and to expose top surface of first etch stop layer, etching first etch stop layer of patterned structure, and forming self-aligned via.

NAIK M, HWANG H D, LANG C, REN H, LU C, JIANG H

Vertical transistor device comprises a channel region comprising least one layer of two-dimensional (2D) material, bottom source/drain region, top source/drain region, and gate structure positioned all around one layer.

CIMINO S, STREHLOW E, PRABHU M, NAYYAR N, REN H, SUN K, PRITCHARD D, YANG H

Vertical transistor device comprises top source/drain region positioned vertically above portion of bottom source/drain region, and vertically oriented semiconductor structure positioned between bottom and top source/drain region.

CIMINO S, STREHLOW E, PRABHU M, NAYYAR N, REN H, SUN K, PRITCHARD D, YANG H

Forming interconnect structure, comprises e.g. etching patterned interconnect stack and first etch stop layer to form first conductive lines and second conductive lines and expose top surface of first etch stop layer and barrier layer.

JIANG H, LU C, REN H, LANG C, HWANG H D, NAIK M

Planar transistor device in electronics industry, has layer of two-dimensional (2D) material whose planar top surface and planar bottom surface that are arranged parallel to planar surface of semiconductor substrate.

PRITCHARD D, YANG H, REN H, NAYYAR N, PRABHU M, STREHLOW E, CIMINO S