国家/地区 日本（5）
IPC部 H（5） B（2） C（2）
IPC大类 H01（5） B82（2） C01（2）
IPC小类 H01L（5） B82Y（2） C01B（2）
IPC H01L021/768（5） H01L023/52（5） H01L023/532（5）
H01L021/28（4） H01L021/3205（4） C01B031/02（2）
H01L021/00（2） H01L021/285（2） H01L023/48（2）
H01L023/522（2） H01L029/15（2）
发明人 WADA M（5）
公开年 2012（4）
申请年 2011（3） 
专利权人 TOSHIBA KK（5）

Semiconductor device, has carbon nanotubes that are formed so that graphene layers are stacked in state in which are inclined depthwise with respect to groove and are doped with one element from sidewalls of carbon nanotubes.

SAITO T, WADA M, ISOBAYASHI A, KAJITA A, MIYAZAKI H, SAKAI T

Graphene interconnection for use in interconnection layer of large scale integration device, has graphene layer formed on catalyst film in interconnection trench and provided with graphene sheets.

SAITO T, WADA M, KAJITA A, SAKATA A

Graphene interconnection of large scale integration (LSI) device, has graphene sheets which are stacked in direction perpendicular to side surfaces of interconnection trench.

SAITO T, WADA M, KAJITA A

Semiconductor device for NAND flash memory comprises insulating layer with trench, interconnect layer in trench having copper and concave portion in the copper, and graphene sheet on inner surface of concave portion.

WADA M, YAMAZAKI Y

Semiconductor device has graphene layer with several graphenes which are laminated vertically.

WADA M, YAMAZAKI Y, KAJITA A, SAKATA A