国家/地区 日本（6） 美国（6）
IPC部 H（6） C（4） B（2）
IPC大类 H01（6） C01（4） B82（2）
IPC小类 H01L（6） C01B（4） B82Y（2）
H01B（2）
IPC H01L021/3205（6） H01L021/768（6） H01L023/532（6）
C01B031/02（4） B82Y030/00（2） H01B005/14（2）
H01L021/28（2） H01L023/48（2） H01L023/522（2）
H01L029/06（2） H01L051/00（2） H01L051/44（2）
发明人 YAMAZAKI Y（6）
公开年 2014（6）
申请年 2013（6） 
专利权人 TOSHIBA KK（6） KAJITA A（2） WADA M（2） YAMAZAKI Y（2）

Semiconductor device has metal interconnect and graphene interconnect that are stacked to one another.

SAKATA A, KITAMURA M, WADA M, KATAGIRI M, YAMAZAKI Y, KAJITA A

Graphene wiring for semiconductor device comprises substrate, catalyst layer on substrate, graphene layer on catalyst layer, and dopant layer which contains atom or molecule in side surface of graphene layer.

MIYAZAKI H, SAKAI T, KATAGIRI M, YAMAZAKI Y, SAKUMA H, SUZUKI M, SAKUMA N

Graphene wiring for semiconductor device, has graphene sheet layer arranged on catalyst layer, where atom or molecule is chosen from nitric acid, phosphoric acid, lithium, sodium, potassium, magnesium and calcium.

MIYAZAKI H, SAKAI T, KATAGIRI M, YAMAZAKI Y, SUZUKI M

Semiconductor device e.g. large scale integration (LSI) has graphene on catalyst metal film and carbon nano-tubes which penetrates contact hole on catalyst metal particles.

KATAGIRI M, YAMAZAKI Y, SAKAI T, SAKUMA N, SUZUKI M, SAKUMA H

Semiconductor device, has roll form graphene layer formed to surround catalyst metal layer and for growing with side surface of catalyst metal layer to set as growth origin, where facet is formed on side surface of catalyst metal layer.

WADA M, YAMAZAKI Y, KAJITA A, ISOBAYASHI A, SAITO T

Semiconductor device has wiring layer which is formed of graphene and in contact with carbon nanotube on upper surface of portion of catalytic layer outside hole so that portions of catalytic layer are perforated and continuous films.

SAITO T, WADA M, ISOBAYASHI A, YAMAZAKI Y, KAJITA A