国家/地区 中国（5）
IPC部 C（2） H（2）
IPC大类 C01（2） H01（2）
IPC小类 C01B（2） H01L（2）
IPC C01B031/04（2） H01L029/06（2）
发明人 YE T（5）
公开年 2012（5）
申请年 2012（4） 
专利权人 UNIV PEKING（4）

Graphene-emitting diode structure for diode logic gate, has rectangle portions that are connected with graphene nanostructures, and graphene nanostructure that is composed of negative type and positive type doping graphene nanostructure.

FU Y, HUANG R, REN L, ZHAO H, WEI Z, ZHANG X, YE T

Preparing graphene nanometer belt for making integrated circuit, involves preparing graphene on substrate, using metal nano-particles, etching along graphene preferred direction in annealing process, in boundary domain function of graphene.

FU Y, HUANG R, WEI Z, ZHANG X, YE T, ZHOU M

Etching of multi-layered graphene involves forming multi-layered graphene on substrate, forming bands with specific height on substrate, annealing substrate by supplying argon/hydrogen, and then naturally cooling substrate.

FU Y, HU B, HUANG R, WEI Z, ZHANG X, YE T

Preparation of atom scale graphene groove, e.g. for nano-electronics field, by suspending graphene on high temperature resistant substrate, depositing metal atoms on surface, etching in argon/hydrogen atmosphere, cooling, and vacuum-drying.

FU Y, HUANG R, LI C, WEI Z, ZHANG X, YE T

Graphene device structure for use in complementary metal oxide semiconductor device, has semiconductor doped region and graphene layer that are formed as drain region and source region of device structure respectively.

LIANG Q, JIN Z, WANG W, ZHONG H, LIU X, ZHU H, YE T