国家/地区 日本（5） 美国（4）
IPC部 C（5）
IPC大类 C01（5）
IPC小类 C01B（5）
IPC C01B032/15（5）
发明人 SAKAI T（5）
公开年 2017（4）
申请年 2016（3） 
专利权人 TOSHIBA KK（5）

Graphene structure for use in a semiconductor device, comprises a multilayer graphene that is laminated with graphene sheets, where three interlayer materials are presented between the graphene sheets of the multilayer graphene.

MIYAZAKI H, YOSHIDA T, KATAGIRI M, YAMAZAKI Y, SAKAI T

Semiconductor device has graphene wiring which is connected to conductive region, and corrosion-proof element which is provided to cover area different from partial area of upper surface of connecting element.

MIYAZAKI H, SAKAI T, ISOBAYASHI A, ISHIKURA T, KAJITA A

Graphene wiring structure comprises multilayered graphene having laminated multiple planar polycrystal graphene sheets, and metal oxyhalide and metal halide which exist in the interlayer of planar polycrystal graphene sheets.

MIYAZAKI H, SAKAI T, KATAGIRI M, YAMAZAKI Y

Semiconductor device e.g. integrated circuit has first graphene layer with stacked structure and has multiple graphene sheets, in which each graphene sheet has depression in central portion.

SAITO T, ISOBAYASHI A, KAJITA A, SAKAI T

Graphene wiring structure has multi-layer graphene portion whose outer surface is physically connected with side surface of orthogonal direction with respect to substrate of insulating film.

SAKAI T, YAMAZAKI Y, MIYAZAKI H, KATAGIRI M, KAJITA A, ISHIKURA T