国家/地区 日本（6）
IPC部 C（6）
IPC大类 C01（6） H01（6）
IPC小类 C01B（6）
IPC C01B031/02（6） H01L021/3205（6） H01L021/768（6）
H01L023/532（6） H01L023/528（4） H01L021/285（2）
发明人 SAKAI T（6）
公开年 2016（6）
申请年 2015（6） 
专利权人 TOSHIBA KK（6）

Manufacture method of semiconductor device, involves forming graphene interconnect by patterning graphene film into which dopant is introduced.

WADA M, YAMAZAKI Y, MIYAZAKI H, KAJITA A, SAITO T, ISOBAYASHI A, ISHIKURA T, KATAGIRI M, SAKAI T

Semiconductor device such as metal oxide semiconductor (MOS) transistor and capacitor, has graphene layer with first graphene layer and is provided on second catalyst region.

SAITO T, KITAMURA M, SAKATA A, WADA M, KAJITA A, SAKAI T

Graphene wiring structure comprises multilayer graphene and interlayer composites provided between layers of multilayer graphene, such that portion of defect and grain boundary of planar graphene sheet are closed.

SAKAI T, MIYAZAKI H, KATAGIRI M, YAMAZAKI Y

Graphene wiring has interlayer cross-linked layer which includes cross-linked molecular structure including multiple bonded molecules cross-linking graphene sheets included in multilayer graphene.

MIYAZAKI H, SAKAI T, YAMAZAKI Y, KATAGIRI M

Wiring used as conductor in semiconductor device (e.g. integrated circuit, or memory chip) or electronic circuit, comprises multilayer graphene including graphene sheets, interlayer substance, and organic compound layer.

MIYAZAKI H, SAKAI T

Method for manufacturing semiconductor device, involves forming first film, pattern of second film on upper surface of first film and graphene film on upper surface of first film and from side surface of pattern of second film.

ISOBAYASHI A, KITAMURA M, YAMAZAKI Y, KAJITA A, SAITO T, ISHIKURA T, SAKATA A, SAKAI T, WADA M