国家/地区 中国（8）
IPC部 H（8）
IPC大类 H01（7）
IPC小类 H01L（6）
IPC H01L029/08（2） H01L029/423（2） H01L029/739（2）
H01L029/78（2）
发明人 WANG W（8）
公开年 2019（5）
申请年 2019（5） 
专利权人 UNIV NANJING POST TELECOM（8）

Inclined magnetic tunnel junction memory based on bismuth selenide-doped lithium atom substrate, comprises top electrode set from up to down sequentially SOT-magnetic tunnel junction and substrate.

ZHOU Z, WANG W, QI Y

Inclined magnetic tunnel junction memory based on bismuth-selenide graphene heterojunction substrate for e.g. reading magnetic head of computer hard disk, has reference layer and free layer that are made of cobalt-iron-boride material.

YANG R, WANG W, LI S

Vertical tunneling transistor based on graphene-molybdenum disulfide heterostructure, used in electronic equipment, has hexagonal boron nitride and substrate which are located below second graphene layer.

JI N, QU K, CHENG Q, WANG W

Tunnel Darner graphene nano-tube, has channel whose two sides are provided with silicon dioxide oxide layer cover channel, source region and drain region, and double gate provided with sub-grid electrode.

WANG Z, QU K, WANG W

Source-drain light doping heterogeneous gate graphene nanometer strip field effect tube, has source region provided with source N-type heavily doped region and source extension region, and gate oxide layer located on two sides of graphene nano-tubes.

ZHANG W, QU K, WANG W

Method for preparing graphene oxide/copper-2,3,6,7,10,11-hexahydroxytriphenylene composite material, involves dissolving graphene oxide nanosheet in dimethylformamide, and adding copper nitrate trihydrate, followed by centrifuging.

ZHAO W, JIN B, ZHAO Q, PENG J, WANG W, CHEN T, LIU S, HUANG W

Metal oxide semiconductor memory comprises silicon substrate, two-layer structure of ultra-thin asymmetric alumina/hafnia as tunnel oxide layer, four-layer graphene nanoflake as charge storage layer, gate oxide layer and gate.

CHENG Q, JI N, QU K, LI G, WANG W

Double-line drain gate oxide layer graphene hetero-doped tunneling FET structure, has FET provided with source electrode and drain electrode, and double-gate connected with intrinsic graphene nano-meter belt and drain oxide layer.

GAO J, WANG W, ZHANG L, YUE G