国家/地区 中国（7）
IPC部 H（6） B（2） C（2）
IPC大类 H01（6） B82（2）
IPC小类 H01L（6） B82Y（2）
IPC H01L021/336（5） B82Y040/00（2） H01L021/28（2）
发明人 WU T（7）
公开年 2014（7）
申请年 2014（4）  2013（3） 
专利权人 SHANGHAI INST MICROSYSTEM INFORMATION（7）

Manufacture of graphene flash memory involves patterning conductive layer formed on semiconductor substrate, forming source/drain electrodes, dielectric layers, graphene layer and gate electrode, and etching dielectric layers.

WANG H, JIANG M, LI L, XIE X, WU T, CHEN J, LU G, XIE H, ZHANG X

Method for preparing flexible substrate of graphene device, involves performing low temperature deposition process to form grid medium layer and performing etching process on gate medium layer.

WANG H, JIANG M, XIE X, WU T, CHEN J, SUN Q, XIE H, ZHANG X

Graphene contact resistance reducing method, involves forming source and drain electrode area on surface of thin film, forming hole in drain metal electrode, forming grid medium layer on film, and fixing gate with grid medium layer.

WANG H, JIANG M, XIE X, WU T, CHEN J, LU G, SUN Q, XIE H, ZHANG X

Graphene FET micro-zone heating method, involves regulating rear gate voltage to modulate edge micro-structure, and performing high-temperature narrow edge micro-structure heating process at temperature of about specific degrees centigrade.

WANG H, XIE X, WU T, XIE H, CHEN J, DENG L, LIU X, SUN Q, ZHANG X

Preparation of graphene crystal domain involves forming copper-nickel double sided substrate, introducing hydrogen, reacting, introducing carbon source, growing graphene crystal domain, introducing argon gas and cooling.

YANG C, WU T, LU G, ZHANG X

Graphene device manufacturing method, involves forming PMMA layer on PVA layer, where thicknesses of PVA layer and PMMA layer are in specific range, and graphene layer formed in PMMA layer.

WANG H, JIANG M, XIE X, WU T, SUN Q, XIE H

Manufacturing method of graphene field effect transistor, involves etching surface of carbon nanotransistor and connecting carbon nanotransistor to sub-electrodes to form graphene nanometer belt on semiconductor substrate.

SUN Q, XIE X, WU T, XIE H, WANG H