国家/地区 美国（7） 韩国（4） 中国（3） 台湾（3）
IPC部 H（8） C（3）
IPC大类 H01（7） C01（2）
IPC小类 H01L（6）
IPC H01L021/768（4） H01L023/532（3） H01L023/522（2）
H01L029/40（2）
发明人 LEE M（9）
公开年 2023（9）
申请年 2022（7） 
专利权人 SAMSUNG ELEC.（3） TAIWAN SEMIC.（3）

Electronic device e.g. semiconductor memory device, for use in memory system, has gate oxide layer formed between resistance switching layer and gate, source and drain that are arranged on switching layer and spaced apart from each other, and color filter arranged on switching layer.

SHIN H, KIM H, HINTON H J, LIU C, HAM D, JANG H, LEE M

Noble metal-manganese oxide composite catalyst for a positive electrode of an aqueous rechargeable battery that regenerates a solvent of an aqueous electrolyte.

LEE M, KIM H, NO W J, JEONG M J, JO H, OH S H, CHO H, JUNG M J, NOJU, KIM H S, LEEMINAH

Piezoresistive composition used to manufacture piezoresistive composite for three dimensional printing and sensor devices, comprises metal-nanocarbon composite particle, polymer e.g. thermoplastic elastomer and organic solvent.

CHOI H J, LEE M, SONG K, PARK S W

Method for manufacturing copper indium gallium selenide solar cell, involves forming graphene layer or montmorillonite layer on substrate, and forming copper indium gallium selenide light absorption layer on rear electrode.

KIM B, KEUM D, LEE M, KEUM D K, WON L M

Manufacture of wiring used in electronic device, involves growing graphene layer on substrate using plasma of hydrocarbon at specific temperature by plasma enhanced chemical vapor deposition, and doping graphene layer with metal.

LEE C, LEE M, SHIN H, BYUN K, KIM K, SHIN K, SHIN K W, KIM K B, BYUN K E, SHIN H J, HYUN L, LEE C S

Semiconductor device has gate electrode, gate dielectric, channel layer with two-dimensional semiconductor material, where at location of gate electrode not vertically overlapping source and drain electrodes, height of gate electrode is defined from lowermost to uppermost surface of gate electrode.

SHIN H, CHO Y, SEOL M, LEE M

Semiconductor structure use in semiconductor integrated circuit industry, has dielectric layer formed on substrate, graphene conductive structure formed with graphene layer, and graphene layer extending direction parallel to inner side surface of dielectric layer.

LI M, LU M, LI S, ZHAN Y, YANG S, GUO Z, LEE M, CHAN Y, KUO T

Method for manufacturing semiconductor structure, involves forming graphene conductive structure on metal layer, where conductive graphene is filled in interconnection channel and electrically connected with contact piece.

LI M, YANG S, ZHAN Y, LI S, ZHONG J, YEH C, LEE M, CHAN Y, CHUNG C

Interconnection structure useful for semiconductor device, has more than one first conductive features disposed in first dielectric layer, where more than one first conductive features include first metal, and multiple graphene layers include second metal, which is different from first metal.

SUI X, LI M, YANG S, ZHAN Y, LI S, SHUE S, LEE M, CHAN Y