国家/地区 中国（16） 世界知识产权组织（3） 美国（2）
IPC部 H（14） C（3）
IPC大类 H01（13） C01（3）
IPC小类 H01L（12） C01B（3）
IPC H01L021/336（5） H01L029/16（4） H01L029/78（4）
C01B031/04（3） H01L021/04（2） H01L021/20（2）
H01L021/28（2） H01L029/06（2） H01L029/08（2）
H01L029/10（2） H01L029/423（2） H01L029/66（2）
发明人 JIN Z（10） MA P（6） SHI J（5）
ZHANG D（5） CHEN J（4） LIANG Q（4）
LIU X（4） PENG S（4） ZHU H（4）
LI C（3） LUO W（3） XIA Y（3）
XIE J（3） ZHONG H（3） CHEN D（2）
公开年 2013（16）
申请年 2013（7）  2012（6）  2011（3） 
专利权人 INST MICROELECTRONICS CHINESE ACAD SCI（16）

Making graphene conductive film involves depositing copper on graphite surface, growing graphene on copper surface followed by adhering heat release adhesive tape on graphite surface, and subjecting to electrochemical etching method.

JIN Z, MA P, ZHANG D, SHI J

MOSFET, has source/drain region formed on semiconductor substrate, and gate conductor extended toward upper part of source/drain region, where semiconductor substrate is formed with oxide semiconductor substrate and graphene layer.

CHEN L, LUO Z, ZHU Z

Graphene oxide top gate FET device parasitic resistance reducing method, involves covering gate-source, forming metal lead contact, and adjusting distance between gate-source and gate drain to reduce channel access resistance.

CHEN J, JIN Z, MA P, PENG S, ZHANG D, SHI J

Graphene conductive film preparation method, involves growing graphene on metal foil surface, and conducting reduction treatment of deposition of metal foil graphene oxide under high temperature condition of protective gas.

JIN Z, MA P, ZHANG D, SHI J

Graphene field effect transistor, has insulating layer formed on semiconductor substrate, and gate electrode located on gate dielectric layer, which is provided with graphene oxide medium layer and metal oxide dielectric layer.

JIN Z, ZHANG D, CHEN J, MA P, PENG S, SHI J

Self-aligned graphene FET, has grid metal layer formed with gate dielectric layer, and self-aligned metal layer covered on source electrode, drain electrode, conductive channel and grid metal layer.

JIN Z, ZHANG D, CHEN J, MA P, PENG S, SHI J

Method for reducing graphene material and contact resistance of metal interconnection structure, involves providing structure using multi-layer graphene in contact area of graphene material and metal using single-layer graphene.

JIN Z, CHEN J, MA P, PENG S, WANG X

Analog-to-digital converter, has multi-path distributor provided with multiple graphene channels and gate contact, where included angle is formed between each graphene channel and gate contact.

JIN Z, LIU X, YE T, CHEN D, LIANG Q, ZHU H, ZHONG H

Graphene device for use as multi-channel selective device, e.g., multiplexer or demultiplexer, has graphene channels which are in contact and electrically connected with gate, in which graphene channels and gate have different angles.

JIN Z, LIANG Q, LIU X, YE T, ZHONG H, ZHU H, CHEN D

Graphene radial direction heterojunction solar battery, has single crystal silicon substrate formed with p-type or n-type silicon nano-passivation film, and mono-crystalline silicon substrate placed with back electrode.

JIA R, JIN Z, CUI D, CHEN C, DING W, LIU X, QIAO X