国家/地区 美国（10） 中国（7） 台湾（6）
IPC部 H（10）
IPC大类 H01（10）
IPC小类 H01L（10）
IPC H01L023/532（6） H01L021/768（5） H01L023/522（5）
H01L023/528（4） H01L029/16（3） H01L029/66（3）
H01L021/76（2） H01L029/06（2） H01L029/10（2）
H01L029/76（2） H01L029/78（2）
发明人 LEE M（5） SHUE S（5） YANG S（5）
LI M（4） SUI X（4） LEE M H（3）
公开年 2021（6） 2020（3）
申请年 2019（10）
专利权人 TAIWAN SEMICONDUCTOR MFG CO LTD（10）

Semiconductor device e.g. integrated circuit used in complementary metal oxide semiconductor (CMOS) logic device, has source or drain contacts that are provided in contact with channel stack, and gate electrode is provided below substrate.

WU C, NI I, HSIAO C, WANG Y, XIAO Z, NI Y, WU Z

Resistive memory device comprises word lines laterally extends along second horizontal direction and laterally spaced apart along first horizontal direction, and selector material layer located between each of word lines.

LI L, CHEN T, CHENG C, CHIANG H, JIANG H, ZHENG Z, CHEN Z

Semiconductor structure for manufacturing integrated circuit (IC) device, has via which electrically couples first conductive feature to second conductive feature, and graphene layer arranged over portion of first conductive feature.

YANG S, CHAN Y, LEE M, CHEN H, SHUE S, LI M, SUI X, LEE M H

Interconnect structure for integrated circuit (IC) device e.g. transistor, has graphene layer which is provided between second contact feature and third dielectric layer.

YANG S, LEE M, SHUE S, LI M, SUI X, LEE M H

Integrated circuit comprises semiconductor substrate, source region with doped semiconductor material, drain region with doped semiconductor material, gate formed between source region and drain region and nanosheet with specific regions.

LIN Y, CHIU Y, CHANG S, TSAI C, HUANG Y, CHENG K, WANG C, QIU Y, ZHANG S, CAI Q, CHENG G, WANG Z

Interconnect structure used to fabricate e.g. transistors comprises first contact feature in first dielectric layer, second dielectric layer, second contact feature over first contact feature, barrier layer between second dielectric layer and second contact feature and carbon layer.

YANG S, LUO G, CHUNG C, LEE M, SHUE S, LI M, SUI X, LEE M H

Method for forming graphene layer, involves performing carbon dissolution process to cause graphene layer to form between seed layer and underlying conductive feature, and filling remainder of trench with conductive material.

YANG S, LEE M, SHUE S, LI M, SUI X

Semiconductor structure has metal line that is located over via and in contact with first graphene layer and second graphene layer peripherally enclosing metal line and first graphene layer which extends along top surface of via.

YANG S, LEE M, SHUE S

Device used for producing graphene films, comprises a graphene layer provided over a concave or convex region of a substrate and planar region of the substrate, concave or convex region and the planar region provided adjacent to each other.

CHEN M, PAN S C, HSIEH C

Method for forming semiconductor device e.g., transistor, involves transforming portion of carbon layer to graphene during annealing, removing metal layer and etching graphene to define channel and source/drain region from graphene.

LIN M, LIN S, LEE S