国家/地区 美国（13） 台湾（9） 中国（7） 德国（3） 韩国（3）
IPC部 H（12） G（3） C（2）
IPC大类 H01（11） C01（2） G03（2）
IPC小类 H01L（11） C01B（2） G03F（2）
IPC H01L021/768（6） H01L029/66（6） H01L023/532（5）
H01L029/16（5） H01L029/78（5） H01L023/522（4）
H01L029/06（4） H01L021/336（3） H01L029/10（3）
H01L029/24（3） H01L029/423（3） H01L029/786（3）
C01B032/182（2） G03F001/62（2） H01L021/34（2）
发明人 KHADERBAD M A（4） LEE M（4） SHUE S（4）
YANG S（4） LIN C（3） SHEN T（3）
CHAN Y（2） GAO C（2） GAU T（2）
HSU P（2） LEE H（2） LI X（2）
LIAN D（2） LIEN T（2） LIN J（2）
公开年 2022（7） 2021（6）
申请年 2021（13）
专利权人 TAIWAN SEMICONDUCTOR MFG CO LTD（13）

Protection assembly for use during optical lithography patterning process, has outer surface and inner surface, which are connected with each other, where conformal coating is formed on outer surface of protective film.

LIN J, GAO C, LI X, LIAN D, XU B, HSU P, LIEN T, LEE H, GAU T, LIN C

Semiconductor device, comprises substrate and fin structure on substrate, and includes epitaxial region, etch stop layer on epitaxial region, interlayer dielectric layer on etch stop layer, and metal contact through etch stop layer and interlayer dielectric layer.

SHEN T, HUANG J, CHEN S, LIN H, LIN C, WOON W, KHADERBAD M A

Semiconductor device e.g. metal oxide semiconductor field effect transistor, comprises graphene film that covers top surface and sidewalls of epitaxial region and covers bottom surface and side walls of metal contact.

WOON W, KHADERBAD M A

Method for forming thin film assembly of film-shaped object, such as semiconductor wafer, involves reducing thickness of film to obtain thin film, and stretching membrane using stretching frame to obtain extended membrane.

LIN J, GAO C, CHEN L, LIAN D, XU B, LI X, LIN C, GAU T, LIEN T, HSU P, LEE H

Forming graphene layer between seed metal layer in integrated circuit, involves forming first contact feature in first dielectric layer over workpiece, forming second dielectric layer over first contact feature and first dielectric layer.

SHUE S, LEE M, YANG S

Semiconductor structure, has graphene layer arranged over first and second conductive features, where sidewalls of second dielectric layer are defined by graphene layer, and metal capping layer is arranged between graphene layer and features.

SHUE S, CHEN H, LEE M, CHAN Y, YANG S

Photon device for high-speed interconnection in light sub-system, has multiple metal layers set on substrate, photon material layer provided with graphene and set on multiple metal layers, and light routing layer provided with waveguide and set on photon material layer.

ISLAM R, RUSU S, SONG W, ISLAM M R

Device, preferably semiconductor device, comprises conductive feature partially disposed within dielectric layer, via electrically connected to conductive feature, graphene layer disposed on conductive feature, and seed layer.

SHUE S, LEE M, YANG S

Method for forming semiconductor device, involves configuring gate structure, source and drain components, semiconductor structure and two-dimensional material layer, and utilizing semiconductor structure and two-dimensional material layer as channels between source and drain components.

SHEN Z, KHADERBAD M A, MA H, SATHAIYA D M, ABHIJITH K M, SHEN T, DHANYAKUMAR S M

Integrated chip includes inner connecting through hole extending through inner connecting dielectric layer, directly configured on protective pad layer, and electrically coupled to inner connecting line, where pad layer comprises graphene.

SUI X, LI M, HUANG X, LU M, ZHAN Y, YANG S, CHAN Y, SHUE S, LEE M, HUANG H, LEE M H