国家/地区 美国（23） 韩国（19） 中国（8） 欧洲专利局（EPO）（8） 日本（2）
IPC部 H（20） C（10） G（2）
IPC大类 H01（20） C01（10） C23（7）
G06（2） H10（2）
IPC小类 H01L（20） C01B（10） C23C（7）
G06N（2） H10B（2）
IPC H01L029/16（10） C01B032/186（9） H01L021/02（9）
H01L029/06（7） C23C016/26（6） H01L021/285（5）
H01L023/532（5） H01L029/423（5） H01L029/786（5）
C01B032/182（4） C23C016/50（4） H01L021/768（4）
C23C016/02（3） C23C016/513（3） H01L021/324（3）
发明人 KIM C（24）
公开年 2023（8） 2020（7） 2021（5） 2022（3）
申请年 2022（7）  2019（5）  2021（5）  2020（4） 
专利权人 SAMSUNG ELECTRONICS CO LTD（24）

Graphene structure for use in semiconductor device, comprises substrate, graphene on surface of substrate, and bonding region, where material of substrate and carbon of the graphene are covalently bonded, between surface of substrate and graphene, where bonding region has silicon carbide.

JUNG A, LEE C, SHIN K, KIM C, SHIN H, SONG H, BYUN K, LEE E

Nonvolatile memory device for neuromorphic apparatus, has gate insulating layer extending in first direction between channel layer and gate electrodes, where each of gate electrodes includes metal-doped graphene.

SHIN K, KIM C, PARK S, KIM H, BYUN K, YUN D, LEE C, LI C, YIN T, PIAO S, JIN C, SHIN K W, PARK S H, KIMHYUNWOO, BYUN K E, JIN Y D, LEE C S

Electronic device for use in electronic apparatus, has two-dimensional material layer formed between channel layer and gate electrode, where material layer blocks electron transfer between gate electrode and channel layer.

SHIN K, BYUN K, LEE S, KIM C, LEE C, LI C, JIN C, SHIN K W, BYUN K E, LEESANGSOO, LEE C S

Graphene interconnect structure useful for electronic device comprises first oxide dielectric layer including porous silicon oxide, or amorphous boron nitride, second oxide dielectric layer including aluminum oxide and graphene layer.

KIM C, BYUN K E, SHIN K W, LEE C S, BAEKWON P, PARK B, LEE C, SHIN K, BYUN K

Forming thin film of transition metal dichalcogenide involves providing substrate in reaction chamber, depositing transition metal dichalcogenide thin film on substrate using sputtering process that uses transition metal precursor and chalcogen precursor and is performing at first temperature.

JUNG J, SOHN A, SHIN H, BYUN K, KIM S, KIM C

Vertical channel array transistor for use in semiconductor device, has graphene insertion layer that is formed between source/drain electrode and channel pattern.

BYUN K, KIM S, KIM C, SHIN K, LEE C, LI C, JIN C, JIN S, BYUN K E, SHIN K W, LEE C S

Multi bridge channel field effect transistor for use in e.g. memories, has gate insulating layer that surrounds first channel layer, and gate electrode that surrounds first channel layer with gate insulating layer.

KIM C, KIM U, JUNG A, BYUN K, JIN Y, JIN C, JUNG A R, BYUN K E

Semiconductor device for use in electronic apparatus, has source/drain structure including silicide film to be formed between first semiconductor region and first electrode, and conductive barrier to be formed.

KIM C, NAM S, SHIN K, LEE D, LI D, JIN C, NAM S G, SHIN K W, LEE D H

Field effect transistor structure comprises a fin-shaped channel protruding from a substrate and extending in one direction, a source electrode on one side of the fin-shaped channel, and a drain electrode separated from the source electrode with the fin-shaped channel.

LEE E, YANG B, KIM S, CHOI T, LEE M, SHIN H, KIM C, SHIN H J, HYUN L, CHOI T J, YANG B S

Neural computer, has image classifier for classifying images received through preprocessor by using data output by flattening unit as input value, where preprocessor includes optical signal processor to receive image and generate feature map.

HAM D, LEE M, SHIN H, HINTON H J, JANG H, KIM C, HENRY H, SHIN H J, HYUN L, HAM D H