国家/地区 美国（10） 韩国（7） 中国（3） 日本（2）
IPC部 H（10） C（3） B（2）
G（2）
IPC大类 H01（10） C23（2）
IPC小类 H01L（10） C23C（2） H01B（2）
IPC H01L023/532（3） H01L029/16（3） H01B001/02（2）
H01B001/04（2） H01B005/14（2） H01L021/02（2）
H01L021/768（2） H01L021/8234（2） H01L023/00（2）
H01L023/538（2） H01L029/41（2） H01L029/43（2）
H01L029/45（2） H01L031/0224（2）
发明人 KIM K（10）
公开年 2023（5） 2017（2）
申请年 2022（5）  2016（2）  2020（2） 
专利权人 SAMSUNG ELECTRONICS CO LTD（10）

Chuck assembly used in semiconductor device fabrication system, comprises chuck base includes lower base and upper base that is on lower base, ceramic plate on upper base, and isolator ring enclosing outer sidewall of lower base.

JUNG U, SHIN M, SUNG D, NA D, KIM D, KIM K, JEONG S, JUNG S H, KIMKYUNGSUN, KIM D W, SUNG D Y, SU S M, JUNGUNGYO

Manufacture of wiring used in electronic device, involves growing graphene layer on substrate using plasma of hydrocarbon at specific temperature by plasma enhanced chemical vapor deposition, and doping graphene layer with metal.

LEE C, LEE M, SHIN H, BYUN K, KIM K, SHIN K, SHIN K W, KIM K B, BYUN K E, SHIN H J, HYUN L, LEE C S

Integrated circuit device comprises substrate including word line trench and first recess adjacent to first side wall portion of inner wall of word line trench, and channel region on inner wall of word line trench, and channel region including first channel region and second channel region.

KIM K, JIN J

Semiconductor devices with improved electrical characteristics e.g. integrated circuits including metal-oxide-semiconductor field effect transistors, has substrate, first interlayer insulating layer on substrate, lower interconnection line in first insulating layer, and upper interconnection line.

JUNG E, YOO S, KIM R, KIM K, LEE J

Interconnect structure for use in electronic device, has graphene-metal barrier including graphene layers and metal particles on grain boundary of each graphene layer and between graphene layers, and conductive layer formed on barrier.

LEE S, SHIN H, KIM H, KIM K, SHIN K

Nonvolatile memory apparatus for e.g. phase-change random access memory, consists of electrode(s), resistive-change material layer, diffusion prevention layer comprising two-dimensional material, and blocking layer.

LEE M, PARK S, SONG H, SHIN H, KIM K, LEE S, KANG Y

Interconnect structure for use in electronic device, has graphene-metal barrier arranged on substrate, where graphene-metal barrier includes graphene layers and metal particles on grain boundary of graphene layers and between layers.

SHIN K, KIM K, KIM H, SHIN H, LEE S, SHIN K W, KIM K B, MI K H, SHIN H J, LEE S H

Transparent electrode for use in e.g. flexible display, has first electrode layer formed on substrate, and second layer formed on first layer, where set of holes is arranged in repetitive array in graphene mesh structure.

WOO Y S, SOHN H, SHIN W, CHO E, KWAK C, PARK H C, CHO Y, KO D, KO W, KIM K, CHO E H, KO D S, WOONG K, YEO R, SUN X, XIN Y, GUO C, PARK H, CAO Y, GAO D, GAO X, KIM G

Transparent electrode used for electronic device e.g. flat panel display, has layer containing thermosetting copolymer and/or combination of polymers, and layer containing graphene, and layer having electroconductive metal nanowire.

PARK H C, CHO Y, YANG D, KWAK C, KIM K, SHIN W, WOO Y S

Graphene transistor for use as radio frequency transistor in hybrid transistor, has cover covering upper surface of source electrode and drain electrode and forming air gap above graphene channel between source electrode and drain electrode.

CHUNG H, CHUNG U, KIM K, CHUNG H J, JOUNG W I, KIM K N, CHUNG U I, JUNG W, JUNG H, KIM G