国家/地区 中国（9）
IPC部 H（5） C（3）
IPC大类 H01（5） C01（2）
IPC小类 H01L（4） C01B（2）
IPC C01B031/04（2） H01L021/336（2） H01L029/16（2）
发明人 MA P（9）
公开年 2013（9）
申请年 2013（9）
专利权人 INST MICROEL.（6） CHINESE ACAD.（2）

Double-network nanocomposite polymer hydrogel for e.g. biomedicine comprises double-network hydrogel containing monomers, and nanoparticles e.g. graphene oxide, halloysite, carbon nanotube, pyrochlore, montmorillonite, and talcum powder.

NI Z, CHEN M, MA P, DONG W, HUANG C

Preparing graphene foam material comprises taking crystalline flake graphite or natural graphite powder, ultrasonically dispersing obtained graphite oxide product in aqueous solution, and adding carbon nanotube with aqueous solution.

WANG C, YANG S, CHEN L, MA P

Making graphene conductive film involves depositing copper on graphite surface, growing graphene on copper surface followed by adhering heat release adhesive tape on graphite surface, and subjecting to electrochemical etching method.

JIN Z, MA P, ZHANG D, SHI J

Graphene oxide top gate FET device parasitic resistance reducing method, involves covering gate-source, forming metal lead contact, and adjusting distance between gate-source and gate drain to reduce channel access resistance.

CHEN J, JIN Z, MA P, PENG S, ZHANG D, SHI J

Graphene conductive film preparation method, involves growing graphene on metal foil surface, and conducting reduction treatment of deposition of metal foil graphene oxide under high temperature condition of protective gas.

JIN Z, MA P, ZHANG D, SHI J

Manufacture of graphene-based foamed material used for e.g. energy storage material, involves preparing graphite oxide, dispersing in furfuryl alcohol solution, adding oxalic acid, impregnating with polymer foam and curing.

CHEN L, MA P, WANG C, YANG S

Graphene field effect transistor, has insulating layer formed on semiconductor substrate, and gate electrode located on gate dielectric layer, which is provided with graphene oxide medium layer and metal oxide dielectric layer.

JIN Z, ZHANG D, CHEN J, MA P, PENG S, SHI J

Self-aligned graphene FET, has grid metal layer formed with gate dielectric layer, and self-aligned metal layer covered on source electrode, drain electrode, conductive channel and grid metal layer.

JIN Z, ZHANG D, CHEN J, MA P, PENG S, SHI J

Method for reducing graphene material and contact resistance of metal interconnection structure, involves providing structure using multi-layer graphene in contact area of graphene material and metal using single-layer graphene.

JIN Z, CHEN J, MA P, PENG S, WANG X