国家/地区 中国（12）
IPC部 H（9） C（3）
IPC大类 H01（9） C23（2）
IPC小类 H01L（8） C23C（2）
IPC H01L021/336（4） H01L021/28（3） C23C016/01（2）
C23C016/26（2） C23C016/56（2） H01L021/285（2）
H01L029/16（2）
发明人 MA P（12）
公开年 2013（6） 2015（4） 2012（2）
申请年 2013（6）  2014（4） 
专利权人 INST MICROELECTRONICS CHINESE ACAD SCI（12）

Method for nondestructively transferring graphene from metal surface to surface of target substrate e.g. glass substrate, involves transferring prepared polymethyl methacrylate/graphene composite film to surface of target substrate.

JIN Z, MA P, WANG X, ZHANG D, SHI J

Forming copper metal surface on substrate by using chemical vapor deposition, involves growing graphene on surface of copper foil and copper electrolyte agar gel, glassy carbon sheet, graphite, conductive glass or indium tin oxide.

JIN Z, MA P, WANG X, ZHANG D, SHI J

Graphene FET device manufacturing method, involves depositing passivation protection layer using selective etching of passivation protecting layer above grid medium layer, and depositing metal forming source on drain metal electrode.

JIN Z, MA P, WANG X, ZHANG D, WANG S, SHI J

Method for aligning graphene for top gate FET device, involves coating metal on source electrode and drain electrode, and connecting graphene top gate FET device body with electric conduction channel and source and drain electrodes.

JIN Z, MA P, WANG X, ZHANG D, WANG S, SHI J

Making graphene conductive film involves depositing copper on graphite surface, growing graphene on copper surface followed by adhering heat release adhesive tape on graphite surface, and subjecting to electrochemical etching method.

JIN Z, MA P, ZHANG D, SHI J

Graphene oxide top gate FET device parasitic resistance reducing method, involves covering gate-source, forming metal lead contact, and adjusting distance between gate-source and gate drain to reduce channel access resistance.

CHEN J, JIN Z, MA P, PENG S, ZHANG D, SHI J

Graphene conductive film preparation method, involves growing graphene on metal foil surface, and conducting reduction treatment of deposition of metal foil graphene oxide under high temperature condition of protective gas.

JIN Z, MA P, ZHANG D, SHI J

Graphene field effect transistor, has insulating layer formed on semiconductor substrate, and gate electrode located on gate dielectric layer, which is provided with graphene oxide medium layer and metal oxide dielectric layer.

JIN Z, ZHANG D, CHEN J, MA P, PENG S, SHI J

Self-aligned graphene FET, has grid metal layer formed with gate dielectric layer, and self-aligned metal layer covered on source electrode, drain electrode, conductive channel and grid metal layer.

JIN Z, ZHANG D, CHEN J, MA P, PENG S, SHI J

Method for reducing graphene material and contact resistance of metal interconnection structure, involves providing structure using multi-layer graphene in contact area of graphene material and metal using single-layer graphene.

JIN Z, CHEN J, MA P, PENG S, WANG X