国家/地区 中国（12）
IPC部 H（10） B（2）
IPC大类 H01（10）
IPC小类 H01L（9）
IPC H01L021/336（5） H01L021/28（2） H01L029/16（2）
H01L029/78（2）
发明人 JIN Z（7） MA P（6） SHI J（5）
ZHANG D（5） ZHU H（5） CHEN J（4）
GU K（4） PENG S（4） NIE P（2）
SU Y（2） YANG J（2）
公开年 2013（7） 2014（4）
申请年 2013（12）
专利权人 INST MICROELECTRONICS CHINESE ACAD SCI（12）

Semiconductor structure manufacturing method, involves forming interlayer medium layer on contact hole of metal-graphene, and filling electric conduction material in contact hole.

LIANG Q, YE T, ZHU H, ZHONG H

Non-standard electrostatic force switch, has substrate fixed with graphene along arrangement direction, and support electrode connected with source and drain electrodes that are electrically connected together.

SU Y, YANG J, ZHU H, NIE P, GU K

Semiconductor device manufacturing method, involves forming graphene layer with substrate layer, where medium layer is formed with upper end of graphene layer and bump structure, and forming mask side wall with etching layer.

ZHU H, GU K

Semiconductor device manufacturing method involves removing dielectric layer and metal layer, so that graphene layer is transferred onto side of another dielectric layer.

ZHU H, GU K

Interconnection structure, has lower-layer wiring structure formed on substrate, and shielding layer formed on lower-layer wiring structure and arranged with graphene part and upper-layer wiring structure.

SU Y, YANG J, ZHU H, NIE P, ZHAO C, GU K

Making graphene conductive film involves depositing copper on graphite surface, growing graphene on copper surface followed by adhering heat release adhesive tape on graphite surface, and subjecting to electrochemical etching method.

JIN Z, MA P, ZHANG D, SHI J

Graphene oxide top gate FET device parasitic resistance reducing method, involves covering gate-source, forming metal lead contact, and adjusting distance between gate-source and gate drain to reduce channel access resistance.

CHEN J, JIN Z, MA P, PENG S, ZHANG D, SHI J

Graphene conductive film preparation method, involves growing graphene on metal foil surface, and conducting reduction treatment of deposition of metal foil graphene oxide under high temperature condition of protective gas.

JIN Z, MA P, ZHANG D, SHI J

Graphene field effect transistor, has insulating layer formed on semiconductor substrate, and gate electrode located on gate dielectric layer, which is provided with graphene oxide medium layer and metal oxide dielectric layer.

JIN Z, ZHANG D, CHEN J, MA P, PENG S, SHI J

Self-aligned graphene FET, has grid metal layer formed with gate dielectric layer, and self-aligned metal layer covered on source electrode, drain electrode, conductive channel and grid metal layer.

JIN Z, ZHANG D, CHEN J, MA P, PENG S, SHI J