国家/地区 美国（72） 中国（38） 台湾（38） 韩国（6） 德国（5）
IPC部 H（69） G（13） C（11）
B（3）
IPC大类 H01（68） G03（10） C01（8）
C23（4） H04（2）
IPC小类 H01L（68） G03F（10） C01B（8）
C23C（4）
IPC H01L021/768（31） H01L023/532（30） H01L023/522（22）
H01L029/66（21） H01L029/16（19） H01L023/528（15）
H01L021/02（14） H01L029/06（13） H01L029/423（13）
H01L029/78（13） H01L029/786（13） H01L029/10（8）
G03F001/62（6） H01L021/285（6） H01L021/336（6）
发明人 LEE M（19） YANG S（19） SHUE S（15）
LI M（12） SUI X（9） LEE H（8）
LIN C（8） CHAN Y（7） LI S（6）
WU C（6） CHENG C（5） LEE M H（5）
LEE S（5） LI X（5） LIN S（5）
公开年 2022（19） 2021（15） 2023（9） 2017（7） 2018（7） 2015（4） 2016（4） 2014（3） 2020（3）
申请年 2022（20）  2021（13）  2019（10）  2016（9）  2015（5）  2017（4）  2020（4）  2013（3）  2014（3） 
专利权人 TAIWAN SEMICONDUCTOR MFG CO LTD（73）

Semiconductor interconnecting structure for semiconductor device, has two conductive features that are disposed on first dielectric layer, etching stopping layer disposed on first dielectric layer, where second dielectric layer is disposed on etching stopping layer.

CHIN S

Semiconductor structure comprises copper conductive structure formed in dielectric layer and below at least one etch stop layer, and bi-layer liner adjacent to copper conductive structure, where bi-layer liner comprises first layer of graphene adjacent to copper conductive structure and second layer.

TSAI M, CHI C, CHANG C, CHIN S

Method for forming pellicle assembly in membrane stretching table utilized in deep ultraviolet lithography for processing semiconductor wafer substrate, involves affixing pellicle membrane to mounting frame to obtain pellicle assembly.

LIN C, LIEN T, LEE H, TSAI P, HSU P

Semiconductor device e.g. memory device or transistor, has two-dimensional material channel layer arranged on substrate, where 2D material passivation layer is arranged on 2D material channel layer, and source/drain contacts are arranged on 2D material passivation layer.

TSAI P, LIN S

Semiconductor structure use in semiconductor integrated circuit industry, has dielectric layer formed on substrate, graphene conductive structure formed with graphene layer, and graphene layer extending direction parallel to inner side surface of dielectric layer.

LI M, LU M, LI S, ZHAN Y, YANG S, GUO Z, LEE M, CHAN Y, KUO T

Method for manufacturing semiconductor structure, involves forming graphene conductive structure on metal layer, where conductive graphene is filled in interconnection channel and electrically connected with contact piece.

LI M, YANG S, ZHAN Y, LI S, ZHONG J, YEH C, LEE M, CHAN Y, CHUNG C

Semiconductor package used in e.g. transistors and diodes, comprises package substrate, semiconductor devices, package ring, cover comprising silicon and thermal interface structure thermally connecting semiconductor devices to cover.

YU C, TUNG C, SHAO T, HSIAO S, WU C, WANG J Y

Interconnection structure, has graphene layer arranged between first graphene layer and second graphene layer, where second graphene layer is arranged between conductive feature and dielectric material.

SUI X, ZHANG X, HUANG X, YANG G, CAI C, LEE S, LI S, SHUE S, CHANG H, HUANG H, YANG K, TSAI C, LEE C

Interconnection structure useful for semiconductor device, has more than one first conductive features disposed in first dielectric layer, where more than one first conductive features include first metal, and multiple graphene layers include second metal, which is different from first metal.

SUI X, LI M, YANG S, ZHAN Y, LI S, SHUE S, LEE M, CHAN Y

Transistor for semiconductor device, has channel layer that comprises graphene layer and hexagonal boron nitride sheets dispersed in graphene layer and arrangement directions of hexagonal boron nitride sheets that are aligned and source/drain region next to gate stack that is obtained.

CHEN Z, CHU Z, CHEN T, CHUU C