国家/地区 美国（25） 中国（3） 德国（2） 英国（2） 韩国（2） 世界知识产权组织（2）
IPC部 H（24） B（12） C（2）
IPC大类 H01（24） B82（10） B32（3）
C01（2）
IPC小类 H01L（24） B82Y（10） B32B（3）
C01B（2）
IPC H01L029/16（11） H01L029/06（9） H01L029/66（9）
B82Y040/00（8） H01L021/02（8） H01L021/20（8）
H01L029/775（7） B82Y099/00（6） H01L029/78（6）
H01L051/05（6） H01L029/10（5） H01L051/00（5）
B82Y030/00（4） H01L021/768（4） H01L029/786（4）
发明人 GRILL A（25）
公开年 2012（10） 2013（5） 2014（4） 2011（2）
申请年 2010（5）  2012（5）  2011（4）  2013（4）  2014（2）  2016（2） 
专利权人 INT BUSINESS.（24） GLOBALFOUNDR.（5） SAMSUNG ELEC.（2）

Forming method of interconnect structure, involves patterning trench in dielectric, forming interconnect in trench embedded in dielectric, and forming wrap-all-around graphene barrier surrounding interconnect.

HUANG H, NOGAMI T, GRILL A, BRIGGS B D, LANZILLO N A, LAVOIE C, SIL D, BHOSALE P, KELLY J

Method for forming e.g. graphene device structure, involves heating layer of material on patterned metal and removing un-reacted patterned metal to expose patterned carbon-based nanostructure layer between source region and drain region.

CHU J O, DIMITRAKOPOULOS C D, GRILL A, MCARDLE T J, PFEIFFER D, SAENGER K L, WISNIEFF R L

Semiconductor structure used for semiconductor devices, has graphene layer with number of graphene monolayers and abutting semiconductor carbide layer and with crystalline orientation along surface normal of top surface of substrate.

CHU J O, DIMITRAKOPOULOS C D, GRILL A, SUNG C

Method for forming semiconductor structure involves overlapping portion of each graphene nanoribbon and located atop portion of each silicon carbide fins and silicon fin, and overlapped by gate structure.

COHEN G M, DIMITRAKOPOULOS C D, GRILL A

Device structure e.g. graphene device structure has spaced apart contact with portion on metal layer and insulating substrate, first patterned carbon-based nanostructure layer with regions are not covered by first patterned metal layer.

CHU J O, DIMITRAKOPOULOS C D, GRILL A, MCARDLE T J, PFEIFFER D, SAENGER K L, WISNIEFF R L

Method for forming interconnect structure for integrated microelectronic circuit, involves forming graphene cap directly on uppermost surface of copper structure.

BONILLA G, DIMITRAKOPOULOS C D, GRILL A, HANNON J B, LIN Q, NEUMAYER D A, OIDA S, OTT J A, PFEIFFER D

Semiconductor structure has graphene nanoribbon in which portion overlapped by gate structure defines channel region of semiconductor structure.

COHEN G, DIMITRAKOPOULOS C D, GRILL A

Manufacture of semiconductor structure used as device channels, involves forming silicon carbide fin having at least bare sidewalls on surface of substrate, forming graphene nanoribbon on each bare sidewall of silicon carbide fin.

COHEN G M, DIMITRAKOPOULOS C D, GRILL A

Method for forming interconnect structure for integrated microelectronic circuit, involves transferring graphene from copper foil, and patterning graphene, so that edges are coincided with vertical sidewall surfaces of copper structure.

BONILLA G, DIMITRAKOPOULOS C D, GRILL A, HANNON J B, LIN Q, NEUMAYER D A, OIDA S, OTT J A, PFEIFFER D

Interconnect structure for integrated microelectronic circuit, has graphene cap which is provided with edges that are vertically coincident with edges of copper structure.

BONILLA G, DIMITRAKOPOULOS C D, GRILL A, HANNON J B, LIN Q, NEUMAYER D A, OIDA S, OTT J A, PFEIFFER D, DIMITRAKOPOULOS C, HANNON J, NEUMAYER D, OTT J, DIMITRAKO P C D, GREER A