国家/地区 美国（33） 韩国（28） 中国（9） 欧洲专利局（EPO）（9） 日本（5）
IPC部 H（32） C（19） B（11）
G（6）
IPC大类 H01（32） C01（17） C23（12）
B82（9） G01（4） B32（3）
B01（2） B05（2） C08（2）
G02（2） H10（2）
IPC小类 H01L（28） C01B（17） C23C（12）
B82Y（7） H01B（7） B82B（4）
B32B（3） B01J（2） B05D（2）
C08K（2） C08L（2） G01B（2）
G01J（2） G01N（2） G02F（2）
IPC C23C016/26（11） H01L029/16（10） C01B032/186（9）
H01L021/02（8） H01B001/04（7） B82Y030/00（6）
C01B031/04（6） H01L021/285（6） C23C016/02（5）
H01L021/20（5） H01L029/66（5） H01L029/78（5）
B82B003/00（4） B82Y040/00（4） C01B031/02（4）
发明人 LEE E（36）
公开年 2021（9） 2020（5） 2022（5） 2023（5） 2011（3） 2012（3） 2013（2）
申请年 2021（9）  2020（5）  2022（5）  2019（4）  2010（3）  2012（3）  2011（2） 
专利权人 SAMSUNG ELECTRONICS CO LTD（36）

Graphene structure for use in semiconductor device, comprises substrate, graphene on surface of substrate, and bonding region, where material of substrate and carbon of the graphene are covalently bonded, between surface of substrate and graphene, where bonding region has silicon carbide.

JUNG A, LEE C, SHIN K, KIM C, SHIN H, SONG H, BYUN K, LEE E

Epitaxy structure comprises substrate having upper surface, upper surface having single crystal structure, two-dimensional material layer provided on upper surface of substrate, and multiple of nanorod light emitting devices provided on upper surface of two-dimensional material layer.

HAN J, LEE E, SHIN D, PARK J, PARK Y, KIM J, KIM N, KONG K, CHOI J, CHOI J H, HO K, KIM N H, KIM J S, PARK Y W, PARKJUNGHOON, HAN J H

Semiconductor element used in various integrated circuit devices, has substrate comprising trench, source region, and drain region, where source region and drain region separated apart from each other by trench, gate insulating layer covering bottom surface and sidewall of trench, gate electrode.

CHO Y, BYUN K, KIM S, LEE E, BYUN K E, CHO Y C

Electronic device has substrate having channel between source and drain, gate electrode and film structure with first ferroelectric layer, crystallization barrier layer and second ferroelectric layer sequentially on channel, where average sizes of crystal grains of ferroelectric layers, is preset.

LEE J, LEE E, BAE H, MOON T, NAM S, JO S, LEE H, LEE Y, HEO J, LI Z, LI Y, XU Z

Electronic device used in ferroelectric materials, comprises channel between source and drain, gate electrode on substrate and facing channel, ferroelectric thin film structure between channel and gate electrode, crystallization barrier layer has dielectric material and second ferroelectric layer.

LEE J, LEE E, BAE H, MOON T, NAM S, JO S, LEE H, LEE Y, HEO J, HEO J S, LEE Y S, LEE H S, NAM S G, MOON T H, YOUL B, HA L, HO L J

Field effect transistor structure comprises a fin-shaped channel protruding from a substrate and extending in one direction, a source electrode on one side of the fin-shaped channel, and a drain electrode separated from the source electrode with the fin-shaped channel.

LEE E, YANG B, KIM S, CHOI T, LEE M, SHIN H, KIM C, SHIN H J, HYUN L, CHOI T J, YANG B S

Nanocrystalline graphene used for complementary metal-oxide-semiconductor process, comprises grains in stack of graphene sheets.

KIM S, BYUN K, CHO Y, SHIN K, LEE E, LEE C, SONG H, SHIN H, YOON J, LEE S, LIM H, BYUN K E, CHO Y C, SHIN K W, LEE C S, SONG H J, SHIN H J, SU Y J, LEE S Y, LIM H S, LI Z, YOUN J, SHEN X, LI C, LI Y, ZHAO L, JIN S

Semiconductor device comprises a substrate, semiconductor layer comprising a two-dimensional (2D) material having a layered structure, and adhesive layer between the substrate and semiconductor layer and having adhesiveness to 2D material.

YOO M, SHIN H, KWON J, LEE E, SEOL M, NGUYEN V L, SHIN H J, YOO M S

Interconnect structure for use in electronic device, has graphene layer formed between semiconductor layer and metal layer, and conductive metal oxide layer provided between graphene and semiconductor layers and covering region.

CHOI T, CHO Y, LEE C, LEE E, SHIN K, SONG H, BYUN K, KIM S, SHIN H, SHIN H J, BYUN K E, SONG H J, SHIN K W, LEE C S, CHO Y C, CHOI T J

Forming graphene product including nanocrystalline graphene by plasma enhanced chemical vapor deposition process, involves growing nanocrystalline graphene directly on substrate using plasma of reaction gas.

LEE E, LEE S, BYUN K, KIM C, LEE C, SHIN H, SHIN K, SONG H