国家/地区 韩国（11） 美国（11） 中国（6） 台湾（4） 欧洲专利局（EPO）（3）
IPC部 H（12） C（7） G（4）
B（3）
IPC大类 H01（12） C08（5） B01（3）
C09（2） G11（2）
IPC小类 H01L（12） C08K（5） C08G（4）
C08L（4） B01D（2） B01J（2）
G11C（2）
IPC H01L021/768（6） C08K003/04（5） H01L023/522（5）
H01L023/532（5） C08L001/02（4） C08L067/02（4）
C08G063/16（3） C08K007/02（3） H01L023/528（3）
H01L029/24（3） H01L029/786（3） C08G063/199（2）
G11C013/00（2） H01L021/02（2） H01L029/10（2）
发明人 LEE M（20）
公开年 2021（20）
申请年 2019（9）  2020（6）  2021（5） 
专利权人 SAMSUNG ELEC.（7） TAIWAN SEMIC.（5） SAMYANG CORP（4） KOREA INST I.（2）
UNIV SEOUL N.（2）

Foldable display device e.g. in TV comprises e.g. heat dissipation substrate disposed on support substrate, including copper and their alloy and heat dissipation coating layer on surface of heat dissipation substrate, includes base resin.

LEE K H, CHOI S, LEE M

Device, preferably semiconductor device, comprises conductive feature partially disposed within dielectric layer, via electrically connected to conductive feature, graphene layer disposed on conductive feature, and seed layer.

SHUE S, LEE M, YANG S

Integrated chip includes inner connecting through hole extending through inner connecting dielectric layer, directly configured on protective pad layer, and electrically coupled to inner connecting line, where pad layer comprises graphene.

SUI X, LI M, HUANG X, LU M, ZHAN Y, YANG S, CHAN Y, SHUE S, LEE M, HUANG H, LEE M H

Two-dimensional (2D) material-based wiring conductive layer contact structure used in 2D material-based FET, comprises semiconducting 2D material wiring, conductive layer, and metallic 2D material layer in contact with semiconducting 2D material wiring and conductive layer.

LEE M, YOO M, SHIN H, SEOL M, SHIN H J, YOO M S, HYUN L

Field effect transistor for use in integrated circuit devices, has source electrode and drain electrode arranged on substrate, gate insulating film for surrounding each of set of channel layers, and gate electrode for surrounding film.

SHIN H, CHO Y, SEOL M, LEE M, HYUN L, CHO Y C, SHIN H J, SHEN X, ZHAO L

Semiconductor device i.e. fin FET, for use in e.g. memories, has channel layer formed on gate dielectric and comprising two-dimensional semiconductor material, and source electrode and drain electrode electrically connected to channel layer.

LEE M, SEOL M, CHO Y, SHIN H

Field effect transistor, has gate insulating layer including insulative, high-dielectric constant, two-dimensional material on channel layer, gate electrode provided on layer, and electrodes electrically connected to channel layer.

LEE M, SEOL M, JANG H W, CHO Y, SHIN H

Pellicle for use in a reticle for protecting a photomask, comprises a metal catalyst layer mounted on a substrate, a barrier layer is mounted between the substrate and the metal catalyst layer, and a pellicle membrane is provided on the metal catalyst layer.

PARK S, JEONG S, SHIN H, LEE M

Selective reduction catalyst useful in power plants comprise carrier including nitrogen-doped graphene oxide or nitrogen-doped reduced graphene oxide and active material including manganese oxide, vanadium oxide and cerium oxide.

HONGDAE K, YE B, HYUN L D, JUNG B, KIM T, LEE M

Manufacturing core-shell structured quantum dots involves preparing carbon source dispersion, adding quantum dot core to carbon source dispersion, and then generating plasma plume from carbon source.

WOONG L J, MIN S W, SOO L, LEE M