国家/地区 中国（10） 美国（2） 世界知识产权组织（2）
IPC部 H（8） G（4）
IPC大类 H01（8） G06（2）
IPC小类 H01L（8）
IPC H01L045/00（4） H01L021/336（2） H01L029/78（2）
发明人 LIU M（10）
公开年 2012（3） 2016（3） 2018（2）
申请年 2015（3）  2010（2）  2018（2） 
专利权人 INST MICROELECTRONICS CHINESE ACAD SCI（10）

Memristor for memristor-based neural morphology calculation chip, has barrier layer located on functional layer, and upper electrode layer that is located on barrier layer, where functional layer is resistive layer.

LIU M, LV H, ZHENG X, LI X, DONG D, YU J, XU X

Gallium oxide-based UV detector, has graphene layer formed on surface of gallium crystal substrate, and ohmic contact electrode formed in graphene layer without contact with surface of gallium oxide crystal substrate.

LONG S, QIN Y, DONG H, HE Q, LIU M

Gallium oxide-based UV detector used in space astronomical telescopes, has graphene layer which is grown on surface of H-type boron nitride that is not in contact with gallium oxide crystal substrate.

LONG S, QIN Y, DONG H, HE Q, LIU M

Bipolar retardant variable storage device, comprises substrate, lower electrode surface, rectification function layer, graphene layer, resistive dielectric layer, and upper electrode, where rectification layer is made of aluminum oxide.

LU N, LV H, LIU M, LIU Q, LIU S, LONG S, WANG Y, ZHANG K, ZHAO X

Non-volatile resistive memory, has graphene barrier layer stopping easily oxidizable metal ions from migrating into inert metal electrode through resistive functional layer under effects of electric field during programming process.

LIU Q, LIU M, SUN H, ZHANG K, LONG S, LV H, BANERJEE W, BENAGI R

Method for calculating cut-off frequency of small signal model of graphene transistor, involves obtaining cut-off frequency of MOSFET, and establishing feedback modification small signal equivalent model.

LU N, LIU M, WANG W, XU G, LI L, WANG L

Storage device, comprises insulating substrate, lower electrode, lower barrier layer graphene, resistive functional layer and upper electrode, where resistive functional layer is located on lower barrier layer graphene.

LV H, LIU M, LIU Q, SUN H, ZHANG K, BENAGI R, BANERJEE W

Graphene oxide doped zinc oxide nanometer thin film manufacturing method, involves absorbing-coating mixed solution on sensitive membrane of device and drying in vacuum to obtain graphene doped zinc oxide nanometer film.

HOU C, HUO Z, LI D, LIU M, LONG S, YAN X, WANG X, ZHANG M, XIE C, ZHOU W

FET, has source and drain contact electrodes and graphene trench region that are linked together, where graphene trench region is formed on upper part of insulating substrate.

LIU X, LIU M, HAN M, JI Z, WANG H, SHANG L

FET, has source/drain contact electrode and graphene trench region formed on insulating medium layer, where source contact and drain contact electrodes are respectively connected with graphene trench region.

LIU X, LIU M, HAN M, JI Z, WANG H, SHANG L