国家/地区 中国（14） 美国（10）
IPC部 H（12） G（7） B（6）
C（5）
IPC大类 H01（12） B82（6） C08（3）
G01（3） G02（3） C12（2）
IPC小类 H01L（9） B82Y（6） C08K（3）
G01N（3） H01P（3） C08G（2）
C08L（2） C12Q（2） G02F（2）
IPC H01L021/336（5） B82Y040/00（3） B82Y099/00（3）
C08K003/04（3） H01L021/28（3） H01L029/78（3）
H01P003/18（3） B82Y005/00（2） C12Q001/68（2）
G01N027/62（2） G01N033/487（2） G02F001/01（2）
H01L021/20（2） H01L029/775（2）
发明人 ZHU W（21）
公开年 2013（10） 2012（8） 2014（3）
申请年 2012（21）
专利权人 INT BUSINESS.（10） UNIV SOUTHEA.（6） PENG H（2） STOLOVITZKY .（2）
UNIV NANCHAN.（2） ZHU W（2）

Insulation gate FET, has graphene conductive layer formed with gate oxide layer and semi-conductor layer, where semi-conductor layer is formed with channel area and cell area.

ZHU W, HU A, LU S, ZHU Y

Method for representing data in e.g. compact disk-ROM of mainframe computer, involves applying first voltage to back gate of graphene-based memory device and second voltage to graphene layer, which is bent into opening of insulation layer.

ZHU W

Forming method for semiconductor device, e.g. complementary metal oxide semiconductor (CMOS) integrated circuits involves forming fuse that includes graphene layer and electrically connected to FET.

ZHU W

Semiconductor device, e.g. electronic fuse, for integrated circuit, has fuse, which includes graphene layer, that is electrically connected to source terminal in substrate of FET.

ZHU W

Method for forming semiconductor pressure sensor device for measuring pressure of gas, involves forming sealing ring around outer sidewalls of electrodes and graphene membrane such that ring encircles entire perimeter region of cavity.

CAI J, WU Y, ZHU W

Nanodevice i.e. graphene nanopore transistor device, for identifying and differentiating biomolecules in e.g. DNA sequencing application, has graphene layer wired to metal pads to form transistor in which transistor current is modulated.

PENG H, STOLOVITZKY G A, ZHU W

Electrically differentiating/identifying bases/biomolecules in nanopore, by filling reservoir and nanopore formed through membrane including e.g. graphene layer with ionic buffer, where layer is wired to metal pads to form transistor.

PENG H, STOLOVITZKY G A, ZHU W, STOROVITZKI G A

Forming graphene-based memory device involves forming opening having depth and width in second insulation layer to expose a portion of first and second graphene layers and to suspend exposed portion of second graphene layer in opening.

ZHU W

Graphene-based memory device e.g. flash memory has initial graphene layer which is configured to bend into opening to contact final graphene layer based on initial electrostatic force.

ZHU W

Semiconductor structure for semiconductor device, has substrate, graphene layer and double layer gate dielectric having alternate lamination of silicon nitride layer and hafnium oxide layer.

DIMITRAKOPOULOS C D, FARMER D B, GRILL A, LIN Y, NEUMAYER D A, PFEIFFER D, ZHU W, DIMITRAKOPOULOS C