国家/地区 日本（19）
IPC部 C（19）
IPC大类 C01（19）
IPC小类 C01B（19）
IPC H01L023/532（19） H01L021/768（18） H01L021/3205（17）
C01B031/02（12） H01L021/28（7） H01L023/522（7）
B82Y030/00（6） C01B032/182（6） C01B032/15（5）
C01B032/18（5） H01L021/285（5） H01L023/528（5）
H01B005/14（3） H01L023/48（3） H01L023/52（3）
发明人 SAKAI T（19）
公开年 2016（6） 2017（4） 2018（3） 2013（2） 2014（2） 2015（2）
申请年 2015（8）  2013（3）  2016（3）  2017（3） 
专利权人 TOSHIBA KK（19）

Graphene wiring structure for use in semiconductor device, has multilayer graphene formed on insulating film, where average particle diameter of graphene crystals is larger than width of multilayer graphene.

MIYAZAKI H, SAKAI T, NISHIDA Y, YOSHIDA T, YAMAZAKI Y, KATAGIRI M, SAKUMA N, SAKUMA H

Wiring for semiconductor device, includes first metal portion, multilayer graphene, and second metal portion which are interposed between conductive portions.

KATAGIRI M, SAITO T, SAKAI T, MIYAZAKI H

Graphene structure for use in a semiconductor device, comprises a multilayer graphene that is laminated with graphene sheets, where three interlayer materials are presented between the graphene sheets of the multilayer graphene.

MIYAZAKI H, YOSHIDA T, KATAGIRI M, YAMAZAKI Y, SAKAI T

Semiconductor device has graphene wiring which is connected to conductive region, and corrosion-proof element which is provided to cover area different from partial area of upper surface of connecting element.

MIYAZAKI H, SAKAI T, ISOBAYASHI A, ISHIKURA T, KAJITA A

Graphene wiring structure comprises multilayered graphene having laminated multiple planar polycrystal graphene sheets, and metal oxyhalide and metal halide which exist in the interlayer of planar polycrystal graphene sheets.

MIYAZAKI H, SAKAI T, KATAGIRI M, YAMAZAKI Y

Semiconductor device e.g. integrated circuit has first graphene layer with stacked structure and has multiple graphene sheets, in which each graphene sheet has depression in central portion.

SAITO T, ISOBAYASHI A, KAJITA A, SAKAI T

Graphene wiring structure has multi-layer graphene portion whose outer surface is physically connected with side surface of orthogonal direction with respect to substrate of insulating film.

SAKAI T, YAMAZAKI Y, MIYAZAKI H, KATAGIRI M, KAJITA A, ISHIKURA T

Manufacture method of semiconductor device, involves forming graphene interconnect by patterning graphene film into which dopant is introduced.

WADA M, YAMAZAKI Y, MIYAZAKI H, KAJITA A, SAITO T, ISOBAYASHI A, ISHIKURA T, KATAGIRI M, SAKAI T

Semiconductor device such as metal oxide semiconductor (MOS) transistor and capacitor, has graphene layer with first graphene layer and is provided on second catalyst region.

SAITO T, KITAMURA M, SAKATA A, WADA M, KAJITA A, SAKAI T

Graphene wiring structure comprises multilayer graphene and interlayer composites provided between layers of multilayer graphene, such that portion of defect and grain boundary of planar graphene sheet are closed.

SAKAI T, MIYAZAKI H, KATAGIRI M, YAMAZAKI Y