国家/地区 美国（15） 中国（12） 台湾（12） 德国（4） 韩国（4）
IPC部 H（15）
IPC大类 H01（15）
IPC小类 H01L（15）
IPC H01L021/768（7） H01L023/532（7） H01L029/78（7）
H01L023/522（6） H01L029/06（6） H01L029/66（6）
H01L021/76（5） H01L029/10（5） H01L029/16（5）
H01L021/336（4） H01L027/092（4） H01L029/24（4）
H01L023/528（3） H01L029/08（3） H01L029/12（3）
发明人 LEE M（5） SHUE S（5） YANG S（5）
LEE M H（4） LI M（4） SUI X（4）
WU C（3） CAI Q（2） CHAN Y（2）
CHEN T（2） CHEN Z（2） CHENG C（2）
CHENG G（2） CHENG K（2） CHIANG H（2）
公开年 2021（15）
申请年 2019（6）  2021（6）  2020（3） 
专利权人 TAIWAN SEMICONDUCTOR MFG CO LTD（15）

Device, preferably semiconductor device, comprises conductive feature partially disposed within dielectric layer, via electrically connected to conductive feature, graphene layer disposed on conductive feature, and seed layer.

SHUE S, LEE M, YANG S

Method for forming semiconductor device, involves configuring gate structure, source and drain components, semiconductor structure and two-dimensional material layer, and utilizing semiconductor structure and two-dimensional material layer as channels between source and drain components.

SHEN Z, KHADERBAD M A, MA H, SATHAIYA D M, ABHIJITH K M, SHEN T, DHANYAKUMAR S M

Integrated chip includes inner connecting through hole extending through inner connecting dielectric layer, directly configured on protective pad layer, and electrically coupled to inner connecting line, where pad layer comprises graphene.

SUI X, LI M, HUANG X, LU M, ZHAN Y, YANG S, CHAN Y, SHUE S, LEE M, HUANG H, LEE M H

Method for forming fin-type field effect transistor device, involves forming convex dielectric fin over substrate, forming channel layer on upper surface of dielectric fin along wall of dielectric fin, and forming channel enhancement layer.

HUNG Y, ZHENG Z, CHEN Z, JIANG H, LI L, CHIANG H, CHEN T, CHENG C, HONGITISE, CENTISEAN, RELANEBELL

Semiconductor device e.g. integrated circuit has layer of deposited capacitor material (DCM) which is set over channel region, dielectric layer that is set over DCM layer, and metallic gate electrode layer which is set over dielectric layer.

HUANG W, TSAI C, CHENG K, WANG C, CAI Q, CHENG G, WANG Z, WANGCHUN H, WANG C H, CHENG K L, TSAI C W, HUANG W C

Memory device used in electronic applications e.g. cell phone comprises substrate, first conductive layer, phase change layer over first conductive layer, selector layer between phase change and first conductive and second conductive layer.

WU C

Using deposition system involves loading wafer into processing chamber equipped with RF system, supplying aromatic hydrocarbon precursor into processing chamber, turning on RF power of RF system to decompose aromatic hydrocarbon precursor into active radicals.

WU C, NI I, HSU Y, HUANG J, XU Y, WU Z

Semiconductor device comprises gate structure above channel element comprising channel layer containing silicon, germanium or semiconductor elements, and channel layer containing two-dimensional material.

KHADERBAD M A, MA H, LIN G, SHEN Z, SATHAIYA D M, LIN K, SHEN T, KARDERBARTMURUNALAPJIT, SATAYYADANYAKUMAHAVIER, SENSORMIN, DHANYKUMAR S M

Semiconductor device e.g. integrated circuit used in complementary metal oxide semiconductor (CMOS) logic device, has source or drain contacts that are provided in contact with channel stack, and gate electrode is provided below substrate.

WU C, NI I, HSIAO C, WANG Y, XIAO Z, NI Y, WU Z

Resistive memory device comprises word lines laterally extends along second horizontal direction and laterally spaced apart along first horizontal direction, and selector material layer located between each of word lines.

LI L, CHEN T, CHENG C, CHIANG H, JIANG H, ZHENG Z, CHEN Z